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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
FEATURES
* 1 differential 3.3V LVPECL output * Crystal oscillator interface designed for 18pF parallel resonant crystals * Crystal input frequency range: 19.33MHz - 30MHz * Output frequency range: 145MHz - 187.5MHz * VCO frequency range: 580MHz - 750MHz * RMS phase jitter at 156.25MHz (1.875MHz - 20MHz): 0.39ps (typical) * 3.3V operating supply * 0C to 70C ambient operating temperature * Industrial temperature information available upon request * Available in both standard and lead-free compliant packages
GENERAL DESCRIPTION
The ICS843251-04 is a 10Gb/12Gb Ethernet Clock Generator and a member of the HiPerClockSTM HiPerClocks TM family of high perfor mance devices from ICS. The ICS843251-04 can synthesize 10 Gigabit Ethernet and 12 Gigabit Ethernet with a 25MHz crystal. It can also generate SATA and 10Gb Fibre Channel reference clock frequencies with the appropriate choice of crystals. The ICS843251-04 has excellent phase jitter performance and is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space.
IC S
CONFIGURATION TABLE
Crystal Frequency (MHz) 25 25
WITH
25MHZ CRYSTAL
N Output Divide 4 4 Output Frequency (MHz) 187.5 156.25 Application 12 Gigabit Ethernet 10 Gigabit Ethernet
Inputs Feedback VCO Frequency Divide (MHz) 30 750 25
WITH
625
CONFIGURATION TABLE
Crystal Frequency (MHz) 20 21.25 24 25.5 30
SELECTABLE CRYSTALS
Inputs VCO Frequency (MHz) 600 637.5 600 637.5 750 N Output Divide 4 4 4 4 4 Output Frequency (MHz) 150 159.375 150 159.375 187.5 Application SATA 10 Gigabit Fibre Channel SATA 10 Gigabit Fibre Channel 12 Gigabit Ethernet
Feedback Divide 30 30 25 25 25
BLOCK DIAGRAM
XTAL_IN
PIN ASSIGNMENT
Phase Detector VCO
580MHz-750MHz
OSC
XTAL_OUT
DIV. N /4
nQ Q
VCCA VEE XTAL_OUT XTAL_IN
1 2 3 4
8 7 6 5
VCC Q nQ FREQ_SEL
0 = /25 (default) 1 = /30
FREQ_SEL Pulldown
ICS843251-04
8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843251AG-04 www.icst.com/products/hiperclocks.html REV. A SEPTEMBER 12, 2005
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Type Power Power Input Input Description Analog supply pin. Negative supply pin. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. Differential clock outputs. LVPECL interface levels. Core supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3, 4 5 6, 7 8 Name VCCA VEE XTAL_OUT, XTAL_IN FREQ_SEL nQ, Q VCC
Output Power
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characterristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k
843251AG-04
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REV. A SEPTEMBER 12, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
4.6V -0.5V to VCC + 0.5V 50mA 100mA 101.7C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, TA=0C TO 70C
Symbol VCC VCCA ICC ICCA IEE Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 TBD TBD TBD Maximum 3.465 3.465 Units V V mA mA mA
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V5%, TA=0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current FREQ_SEL FREQ_SEL FREQ_SEL FREQ_SEL VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V -5 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 Units V V A A
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V5%, TA=0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
843251AG-04
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REV. A SEPTEMBER 12, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Test Conditions Minimum 19.33 Typical Fundamental 30 50 7 1 MHz pF mW Maximum Units
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V5%, TA=0C TO 70C
Symbol fOUT Parameter Output Frequency 156.25MHz @ Integration Range: 1.875MHz - 20MHz 159.375MHz @ Integration Range: 1.875MHz - 20MHz 187.5MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% Test Conditions Minimum 145 0.39 TBD 0.48 340 50 Typical Maximum 187.5 Units MHz ps ps ps ps %
tjit(O)
RMS Phase Jitter (Random); NOTE 1
tR / tF
Output Rise/Fall Time
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section.
843251AG-04
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REV. A SEPTEMBER 12, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
Phase Noise Plot
LVPECL
nQx
Noise Power
V CC
Qx
SCOPE
Phase Noise Mask
VEE
f1 Offset Frequency f2
-1.3V 0.165V
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQ0 Q0
t PW
t
PERIOD
80% Clock Outputs
x 100%
80% VSW I N G
20% tR tF
20%
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
843251AG-04
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REV. A SEPTEMBER 12, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843251-04 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin. The 10 resistor can also be replaced by a ferrite bead.
3.3V VCC .01F 10
V CCA .01F 10F
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843251-04 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p
Figure 2. CRYSTAL INPUt INTERFACE
843251AG-04
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REV. A SEPTEMBER 12, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
Zo = 50 84 84
1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
843251AG-04
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REV. A SEPTEMBER 12, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
TRANSISTOR COUNT
The transistor count for ICS843251-04 is: 1891
843251AG-04
www.icst.com/products/hiperclocks.html
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REV. A SEPTEMBER 12, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
8 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 8 1.20 0.15 1.05 0.30 0.20 3.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
843251AG-04
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REV. A SEPTEMBER 12, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Marking 51A04 51A04 1A04L 1A04L Package 8 Lead TSSOP 8 Lead TSSOP 8 Lead "Lead-Free" TSSOP 8 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS843251AG-04 ICS843251AG-04T ICS843251AG-04LF ICS843251AG-04LFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843251AG-04
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REV. A SEPTEMBER 12, 2005

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